Up to now the Dynamic Random Memory (DRAM) interface uses a parallel link, as defined in several JDEC standards, e.g. JEDEC (Joint Electron Device Engineering Council) DDR1/DDR2/DDR3, JEDEC LPDDR1/LPDDR2, JEDEC GDDR3/GDDR4/GDDR5.
Memory interface (also referred to as memory bus) requires more and more bandwidth between a host (e.g. a processor) and the memory device. Indeed, as discussed in the United States Patent Application 2006/0136658, random access memory (RAM) plays a critical role in the operation of computing systems. The performance of computing systems and the software applications executed thereon depends on both the capacity and the speed of the RAM modules used. As software applications become more complex and work with larger amounts of data, RAM modules having both larger capacities and higher speeds are needed. While some improvement in performance can be attained by increasing the density and improving the quality of the memory integrated circuits used to make the RAM modules, new memory interface are required to meet the continually increasing demands of software applications.
It is illustrated in FIG. 1 a diagram showing forecasts of the needs for new DRAM interfaces with larger bandwidth.
Synchronous dynamic random access memory (SDRAM) has been developed to provide high performance memory modules. Among the different implementations of SDRAM, the JEDEC has established standards for double data rate (DDR), e.g. SDRAM, DDR2 SDRAM, DDR3 SDRAM, (low power double data rate) LPDDR SDRAM and LPDDR2 SDRAM. Referring to FIG. 3, it is shown a chronogram that represents a detailed schema of the functioning of a SDRAM memory.
DDR, DDR2, DDR3, LPDDR, LPDDR SDRAM are memory architectures which potentially double the rate of data transfers by utilizing both the rising and falling edges of each clock cycle for transferring data.
United States Patent Application 2006/0018178 discloses a schematic circuit block diagram (illustrated in FIG. 2) showing a prior art data communication circuit of a SDRAM. In FIG. 2, the prior data communication circuit 100 of the SDRAM comprises a plurality of control lines 110, such as /CS (Chip Select), /RAS (Row Address Strobe), /CAS (Column Address Strobe), /WE (Write Enable), and so on, for transmitting control signals to the SDRAM 102. The data communication circuit 100 also comprises address lines 120 and data lines 130. The address lines 120 transmit address signals from the data communication circuit 100 to the SDRAM 102. The data lines 130 transmit data from the data communication circuit 100 to the SDRAM 102. The data lines 130 of the data communication circuit 100 are coupled to the data pins, Q1-QN, of the SDRAM 102. Generally, each of the data lines 130 of the data communication circuit 100 is coupled to each of the data pins, Q1-QN, of the SDRAM 102, respectively. The number of the data lines 130 represents the width of the data bus of the data communication circuit 100. As well, the DRAM interface returns the path of data lines 130 to provide a bidirectional path.
However, it becomes difficult to double the highest defined bandwidth today with a full swing signal and not terminated path. Indeed, the increase of the bandwidth is in general performed by increasing the frequency at which the signals are transmitted, which consequently involves integrity problems for the transmitted signals. Consequently, signal integrity constrains the physical (PHY) layer, and therefore the package, and as a result, the development and material cost is increased. Furthermore, the increase of the bandwidth is also accompanied with an increase of the power consumption. Indeed, power consumption (and heat to be dissipated) increases with the speed, e.g. above 500 mW for latest LPDDR3 32 bit interface. This does not fit with low power system (e.g. mobile phone, laptop) wherein the electrical consumption and heat dissipation is critical.
Differential DRAM interface solutions double the pin number for the same data rate because these solutions rely on two separate wires for sending signals. As the DRAM interface returns the path, in differential mode, that feature (that is, DRAM interface returns the path) increases the design complexity of the PHY layer because the number of pins is doubled, and therefore increases the production costs. Moreover, these solutions further add latency in the transmission of signals.
In such high speed link, errors become frequent and so degrade bandwidth performances. In order to avoid these disadvantages, error correction have been introduced to recover from these errors, e.g. in GDDR5 (Graphics Double Data Rate) supported by JEDEC. The current GDDR5 interfaces use a side band pin to indicate the happening of error during the data transfer between two devices. Again, adding a new pin contributes to the increase of the production cost and PHY layer complexity.
Increasing the bandwidth of DRAM interface is therefore particularly power consuming and leads to degradation of the signal integrity. As energy saving is critical for electronic mobile communication devices and reduction of energy consumption of these devices is currently a major concern, there is therefore a need for a solution permitting to reduce the energy consumption of DRAM interface while increasing the bandwidth of the DRAM interface.